The present invention relates to a memory circuit, and more particularly to a semiconductor memory circuit employing DRAM's and operable in page-mode.
Generally, for performance reasons, system memories are implemented using dynamic random access memories, DRAM's, since they afford high densities (up to 262,144 bits per chip), good performance, and they are reasonably priced compared to alternate technologies. These memories may be operated in page-mode. For purposes of this application a "page" refers to all of the storage cells (bits) of a given row of a DRAM. Most advantageously, page-mode operation is used in applications where memory locations are always accessed sequentially. In computer main memories, accesses are not always sequential, but tend to be sequential to a degree which provides a significant performance advantage. Generally, to operate a DRAM in non-page mode, the row address strobe signal RAS and the column address strobe CAS are activated for each memory access. Recent improvements in memory accessing have been achieved with the recognition that the signal RAS may be held active during a page-mode access and the signal CAS toggled with the next column address being applied to the address bus. As long as addressing is directed to the same page (or row) the RAS signal may be held active and accessing can be accomplished using the CAS signal to column address the memory.
In a specification manual entitled, 1984 Memory Data Book by FUJITSU pgs. 1-7, 1-8, and 1-10, there is provided a description of the page-mode operation of MB8117-10/MB8117-12 memory devices. The page-mode operation is described as permitting the strobing of the column address into the MB8117 while maintaining the signal RAS at a logic "low" level throughout all successive memory operations in which the row address doesn't change.
In an INTEL application note AP-170 entitled, "Intel.RTM. 51C64 and 51C65 CHMOS-D 111 65K Dynamic RAM Device Descriptions" (pgs. 16-18), there is described a Ripplemode.TM. operation wherein the cycle executes by maintaining RAS low while successive CAS cycles are performed. The column address buffer acts as a flow through latch while CAS is high. The data access begins from the time valid column addresses appear on the address bus, rather than from the time CAS occurs.
A patent of interest for its teaching is; U.S. Pat. No. 4,429,375 entitled "Consecutive Addressing of a Semiconductor Memory" by S. Kobayashi, wherein a system is described that uses a shift register to take in column address information at the time the memory cell is accessed. Thereafter in a "consecutive access mode", controlled only by the CAS clock, memory cells having consecutive addresses along the row direction, starting with the address taken in during the preceding RAS/CAS cycle, are accessed, bit-by-bit, by the shift register with each CAS clock signal bumping the column address stored therein without waiting for the column address information to be available through a column address buffer.
Another patent of interest for its teaching of column addressing is; U.S. Pat. No. 4,485,461 entitled "Memory Circuit" by S. Kobayashi. Within that patent there is taught the technique of performing consecutive write operations by entering the "consecutive access mode" which is controlled only by the CAS signal while holding the RAS signal in the active level. Memory cells having consecutive addresses along the row direction will thereby be addressed in turn and data written into the memory cells. This patent is the sequel to the aforementioned patent #375 wherein the page-mode read operation is disclosed. The gist of the two aforereferenced patents is that the generation of the column address information, upon every activation of the CAS signal, as in the case of prior art page-mode systems, is not necessary. On the basis of the column address information taken in at the cycle just prior to the institution of the consecutive address mode, a shift register starts the transfer of the decoded information for each bit, and the decoders will be consecutively selected, thus the time required for the latching operation of the column address information by means of a column address buffer, and the time for the operation of the decoders by means of the sequentially amplified and produced address binary codes, is omitted.